Conventionally, various types of semiconductor devices which store therein a single semiconductor chip 51 as shown in FIG. 8 and FIG. 9 have been proposed (referred to as Prior Art 1). Such a semiconductor device is generally manufactured in the following manner. On a die pad 55 of a lead frame 54, a semiconductor chip 51 is mounted using a thermosetting die-attach material 53 such as silver paste, etc. (hereinafter referred to as die-bonding). Then, the die-attach material 53 is hardened by a heat treatment to fix the semiconductor chip onto the die pad 55 (bonding process).
Thereafter, electrode pads 52 formed on an element forming face of the semiconductor chip 51 are electrically connected to inner leads 56 formed in the lead frame 54 by means of bonding wires 59 such as gold wires, etc., (wire-bonding process). Further, after the above members are sealed with a sealing resin 60, a tie bar (not shown) (the blocking section of the sealing resin 60) formed in the lead frame 54 and support leads 58 for supporting the die pad 55 are cut off, and outer leads 57 are bent (formed) in a shape as desired, thereby preparing a semiconductor device.
In recent years, to meet demands for more compact and lighter weight electric apparatuses, as shown in FIG. 10 and FIG. 11, various 2-chip 1-package semiconductor devices (Prior Art 2) whereon the semiconductor chips 51a and 51b of the same or different sizes are mounted on respective surfaces of the die pad 55 have been adopted. Such a semiconductor device is manufactured, for example, by the method disclosed by Japanese Unexamined Patent Publication 213412/1996 (Tokukaihei 8-213412) wherein the respective rear surfaces (the other faces of the element forming faces) of the semiconductor chips 51a and 51b face each other.
Namely, on one surface of the die pad 55, a semiconductor chip 51a is mounted using a paste-like die-attach material 53a such as silver or non-silver paste, etc. Then, the die-attach material 53a is cured under an applied heat to fix the semiconductor chip 51a onto the die pad 55. Thereafter, a semiconductor chip 51b is mounted using a paste-like die-attach material 53b. Then, the die-attach material 53b is cured under an applied heat to connect the semiconductor chip 51a to the die pad 55.
Thereafter, the electrode pads 52a of the semiconductor chip 51a and the inner leads 56 are wire-bonded by the bonding wires 59a such as gold wires, etc. For the other semiconductor chip 51b, in the described manner, the electrode pads 52b and the inner leads 56 are wire-bonded by the bonding wires 59b. Subsequent processing is the same as the described technique of Prior Art 1.
In the arrangement of the conventional 2-chip 1-package semiconductor device on which the semiconductor chips 51a and 51b of different sizes are mounted, however, the following problems arise when manufacturing the semiconductor device.
Generally, as shown in FIG. 12, the process of sealing with resin is performed by setting the lead frame 54 (see FIG. 10) to a resin sealing mold 64 which includes a cavity 61 for forming the outer shape of the semiconductor device, an injection gate 62 for injecting therethrough the sealing resin 60, and an air vent 63 for deaerating the cavity 61.
When injecting the sealing resin 60 in the cavity 61 from the injecting position P under an applied substantially high pressure, due to the difference in size of the semiconductor chips 51a and 51b, the respective flow rates of the sealing resin 60 in a vicinity of the semiconductor chips 51a and 51b differ, and the sealing resin 60 becomes off-balance. Therefore, the balance of the die pad 55 is distorted, and the die pad 55 deviates in the direction vertical to the surface of the lead frame 54. As a result, the bonding wires 59a and 59b are exposed to the outside of the package (semiconductor device), or the bonding wires themselves are disconnected. Moreover, the semiconductor chips 51a and 51b are exposed to the outside of the package, and the yield of the device is lowered. A resulting inferior appearance with the bonding wires 59a and 59b exposed to the outside of the package is observed in nearly 80 percent of the devices thus manufactured.
In recent years, there is a tendency of adopting thinner chips, die pads 55 or lead frames 54 to meet an increasing demand for a thinner package, and therefore the described problems have become more noticeable.
In order to solve the described problems, it is necessary to maintain the flow rate of the sealing resin 60 in the vicinity of the semiconductor chip 51a substantially equivalent to the flow rate of the sealing resin 60 in the vicinity of the semiconductor chip 51b to ensure a well-balanced state of the die pad 55.
For example, it may be arranged so as to bend the support leads 58 beforehand, and displace the die pads 55 in the vertical direction beforehand with respect to the surface of the lead frame 54. However, in the 2-chip 1-package semiconductor device, it is difficult to ensure the mechanical precision for adjusting a fine offset (displacement) of several tens micron order.
For example, the respective thicknesses of the semiconductor chips 51a and 51b to be sealed in one semiconductor device have been considered. In this method, however, it is difficult to control the manufacturing process.
For example, Japanese Unexamined Patent Publication No. 106961/1992 (Tokukaihei 4-106961) discloses a 1-chip 1-package optical semiconductor device wherein a CCD (charge coupled element), etc., is formed using transparent sealing resin. In this semiconductor device, a semiconductor chip is mounted in such a manner that the side of the semiconductor chip is in alignment with the side of the die pad or it is placed outside of the die pad. This permits voids generated when injecting the resin to be released, thereby preventing a drop in yield by the inferior appearance.
The voids indicate bubbles which hinder the entering of light, especially at the blind spot when seen from the injection gate, i.e., on the opposite side of the injection gate in the cavity. However, the described arrangement of the above publication eliminates the problem of generating voids at the above position.
In order to avoid a drop in yield of the 2-chip 1-package semiconductor device, one may apply the described arrangement for 1-chip 1-package semiconductor device to 2-chip 1-package semiconductor devices. Namely, semiconductor chips may be mounted in such a manner that respective end faces of the semiconductor chips of different sizes are in alignment with the end faces of the die pad or are placed outside the die pad.
However, in the described method, a still greater deviation of the die pad than that occurred in the arrangement of FIG. 12 would occur. Additionally, as described earlier, in the 2-chip 1-package semiconductor device, different from the 1-chip 1-package semiconductor device, it is difficult to adjust the offset for suppressing deviations in the die pad.
When adopting the described method, it is required to set such that the die-attach material for mounting each semiconductor chip to the die pad is not protruded from the die pad. Therefore, only a small amount of the die-attach material can be used. For this reason, in the case of mounting a semiconductor chip of a small size, it is very likely that the semiconductor chip is separated from the die pad when wire-bonding. Additionally, in the case where the semiconductor chip is mounted so that the end face of the semiconductor chip is exposed to the outside of the die pad, it is more likely that the problem of separating the semiconductor chip from the die pad occurs.